In general, most computer system clock distribution is provided by a master oscillator signal driving a large fan out tree to create the required number of clocks to drive the entire system. However, the clock distributions for most systems require a very small time delay (skew) between the clock signal transitions at different chips on different circuit boards, as well as the ability to start and stop various groups of clocks. Multiple copies of the clock signals may be provided by a gate array on each board to "fan out" the copies of the clock. The process variations of the gate array will typically cause different arrays and therefore each circuit board to have different propagation delays, while maintaining a small variation of delay between similar paths in the same array. As a result, the clock cycle is lengthened to accommodate the expected variations in propagation delay.
The problems of clock skew errors accumulate, ultimately offsetting or limiting the improvement possible in a computer system. Techniques for clock frequency multiplication have been used which delay the master reference and XOR the delayed clock with the original. Unfortunately, the rise/fall time effects as well as previously mentioned variances of tolerances of the gate array cause the resulting signal to be nonsymmetric (i.e., each consecutive pairs of cycles not having the same period).
Moreover, computer systems frequently require clocking signals at frequency multiples of the reference or master clock signal, and the previously mentioned clock signal distribution problems are exacerbated at higher frequencies.